The electrification of automobiles has driven an explosive growth in demand for silicon carbide (SiC) power devices, but it has also brought challenges in detecting and identifying defects in these chips. At the same time, there is a growing awareness of how immature SiC technology still is, how much work remains to be done, and how quickly this must be achieved. Automakers are aggressively moving into electric vehicles, and the transition from 400V battery systems to 800V battery systems is accelerating the shift from IGBT devices to SiC devices in electric vehicle power modules. The result will be exponential growth in demand for SiC, all of which needs to function flawlessly. To meet the growing demand for SiC, the industry needs to increase production. This means addressing manufacturing challenges that have long slowed SiC production. These challenges include high equipment costs, as well as defect and reliability issues. To tackle cost issues, SiC substrate manufacturers are moving from 150mm wafers to 200mm wafers. However, this expected exponential growth poses challenges for SiC device screening, which will require innovation from manufacturers, inspection, and test suppliers. Inspection and Metrology Methods A key difference between silicon and SiC power ICs relates to substrate growth. As a uniform crystalline structure, silicon has few subsurface defects. In contrast, silicon carbide is grown via chemical vapor deposition, which leads to extensive subsurface defects such as stacking faults and micropipes. During subsequent epitaxial growth, crystal dislocations can propagate. Additionally, because SiC is a brittle material, it is more susceptible to surface defects like scratches and pits, which can affect the entire chip. Furthermore, SiC chips are prone to cracking during processing, and sawing into dies introduces more opportunities for cracks that can propagate. Therefore, inspection throughout the wafer and assembly processes is critical. Due to their high throughput, engineers primarily rely on optical inspection systems in SiC manufacturing. Many companies offer specialized optical inspection tools for SiC, including review and classification capabilities. Metrology is less straightforward. Metrology feedback involves various parameters that process engineers need to measure, including substrate flatness and thickness, lattice orientation, resistance, and surface roughness. These, in turn, require a diverse set of systems. Sandra Bergmann, Product Manager for Bruker’s White Light Interferometers, stated: “White Light Interferometer (WLI) profilers are used on-site by substrate manufacturers for quality assurance/quality control to measure wafer roughness (sub-nm) of Si, GaN, and SiC. The production of SiC substrates is more challenging. Due to its hardness, polishing is difficult. Therefore, WLI is crucial for optimizing/tracking the polishing process.” SiC devices can be based on planar or trench technologies. WLI is particularly useful for trench depth measurements. Bergmann said: “For high-aspect-ratio trench depth measurements in high-voltage IC processes, WLI can resolve depths from 2µm openings to 40µm. It is non-destructive and allows parallel inspection of all trenches within the field of view. We typically use a 5x objective and a 0.5mm² interrogation field. We also provide full variation of trench depth across the entire field of view.” Wafer inspection needs to consider both surface and subsurface defects, with the latter being particularly important for SiC. Burhan Ali, Product Marketing Manager for Inspection at Onto Innovation, noted: “Optical inspection techniques are used for defect detection, while X-ray and photoluminescence are used for metrology. The challenge with optical inspection is that it effectively finds surface defects at high throughput, but it quickly loses momentum when it comes to subsurface crystal defects. In this case, photoluminescence has proven effective in detecting subsurface crystal defects on SiC substrates and epitaxial layers.” Inspection occurs throughout the assembly process. Optical methods are preferred due to high throughput and low equipment investment but are limited to surface defects. For detecting moderate to high densities of subsurface defects, X-ray is the preferred solution as it can operate at high speeds in 2D. Meanwhile, acoustic inspection can easily detect delaminations but requires parts to be immersed in water. George Harris, Vice President of Global Test Services at Amkor Technology, explained: “Manual, optical, and X-ray inspections are all non-destructive testing methods. Basic X-ray inspection helps review package integrity. A large percentage of system defect modes are easily identifiable with X-ray, making it popular with customers. Depending on customer requirements, destructive mechanical cross-sectioning and scanning electron microscopy of packages can be performed in specialized failure analysis laboratories.” Inspection is not limited to electrical issues. It can also identify defects that may affect thermal management. Brad Perkins, Product Line Director at Nordson Test & Inspection, said: “In packaging, most electrical defects are related to wires crossing/contacting the molding process and causing short circuits. Thermal protection also needs to be considered, which is why engineers inspect die attach, as it is part of thermal management. Excessively large voids, too high a total void percentage, or sufficiently large delaminations will lead to hot spots in the die, resulting in premature failure. Because many power devices are used in high-reliability applications (automotive, trains, windmills, etc.), the cost of failure can be very high, so inspecting for defects that could cause premature field failures is cost-effective for manufacturers.” Test Methods Mass production of SiC is relatively new, as is its application in automobiles. Consequently, rigorous testing processes are being developed to ensure quality and reliability. Testing is conducted across various temperatures, voltages, and frequencies. This is critical because defects may appear benign at lower frequencies and voltages but manifest at higher frequencies and/or voltages. Due to their analog nature, power ICs require both functional and performance testing. For power ICs, testing is divided into static and dynamic tests, i.e., DC and AC. Static testing is performed at room temperature, while dynamic testing is conducted at high temperatures. Fabio Marino, Managing Director of Advantest Italy, stated: “Static testing is no longer a challenge because the Device Under Test (DUT) is tested under steady-state conditions. This means low power. Even for ultra-high voltages, it is low current, and if it is ultra-high current, it is low voltage. The real challenge facing the engineering community is dynamic testing. Dynamic testing is very high power because it tests the DUT’s transition from ON to OFF states and vice versa. This means very high current at very high voltage in a very short time, resulting in extremely high power.” Reliability issues observed in wide-bandgap devices related to gate threshold drift have also driven rigorous testing. NI’s Heidemann noted: “Regarding testing, qualification, and EoL, we need to conduct more thorough testing and delve deeper into device characteristics. For example, gate drift, a phenomenon unique to wide-bandgap devices, varies significantly among different market players. Some exhibit significant drift over the lifetime of an automobile, while others show minimal drift. Interestingly, even within the same supplier, different devices can behave differently. Therefore, there is a greater need for comprehensive testing, including EoL and qualification, which is more demanding compared to the silicon world.” Today, chip test cells cannot perform dynamic testing because chip chucks have very high stray inductance. Engineers only use wafer-level static testing. Even then, due to the application of high voltages, there is a risk of arcing, which can damage good devices. Tom Tran, Product Manager for Power Discretes at Teradyne, said: “Because this is a physical challenge, it has been handled the same way for years—by managing air gaps and, of course, managing the air. As voltages start to climb to 400V and beyond, we typically see a shift from just using physical spacing to adding compressed dry air (CDA) through a pressure chamber that sits紧贴 the wafer.” Current limitations in wafer testing have driven the development of die testing. Advantest’s Marino said: “Power modules are the most robust packaged components we can test both statically and dynamically. But the downside is that these packages contain multiple switches—6 to 48. If one switch fails, you discard the entire package, which is very expensive. That’s why customers are moving to intermediate testing of substrates, for example, before final assembly. It’s slightly cheaper, but you still have 6 to 48 devices. The breakthrough innovation is testing bare dies. This screens each switch (both static and dynamic testing). Only with tested dies do customers benefit in terms of assembly costs.” Bare die testing carries the risk of damaging the probe card and/or ATE if a failing bare die draws high current. But engineers have found ways to address this. Marino explained: “In the transition to bare dies, CREA (now part of Advantest) developed a proprietary technology specifically for this—Probe Card Interface (PCI). It is a hardware and software algorithm that detects abnormal current consumption. Probe cards for testing bare dies have 3000 pins per die, as each pin can only drive 1 amp. Between the tester and the probe card is the PCI, a hardware box. The PCI monitors the current in each pin or group of pins in the probe card. If there is an abnormal current distribution or current consumption (due to a faulty part), the PCI immediately shuts down the power. The part fails, but the chuck, probe card, and tester are protected.” Once dies are assembled into packages, testing can screen for package-related defects as well as those that manifest in dynamic testing. Teradyne’s Tran stated: “In addition to partial discharge testing, package-specific defect mechanisms are typically tested by behavioral changes from wafer to package-level testing. While partial discharge focuses more on packaging and material aspects, electrical testing can reveal physical failures during packaging, such as continuity errors from damaged wire bonds or damage from singulation. Screening can also be performed by examining mean shifts and distributions from wafer sort to final package test.” Detection of reliability-related defects is crucial, and existing standards guide testing for part qualification and production manufacturing. NI’s Heidemann said: “We employ various test methods for EoL and qualification purposes. For qualification, industry standards such as JEDEC and ECPE’s AQG324 define dynamic test scenarios specifically for silicon carbide to introduce new materials with different failure models. Therefore, qualification requires extensive dynamic testing, including dynamic H3TRB, DGS, and DRB tests, which are relatively new compared to IGBTs. Similarly, in end-of-line environments, a wide variety of dynamic test scenarios can be observed, varying among different customers. However, it can be said that end-of-line testing extensively involves dynamic testing under high-temperature and high-voltage conditions. The goal is to ensure these devices are dynamically tested to prevent failure impacts across the production fleet.” Domestic Self-developed Third-Generation Semiconductor Wafer Defect Inspection Equipment Achieves Delivery In January, CETC Fenghua Information Equipment Co., Ltd. launched its first third-generation semiconductor wafer defect inspection equipment with fully independent intellectual property rights—Mars 4410. Currently, the equipment has been shipped to multiple domestic customers for use. Mars 4410 is a key piece of equipment in SiC device production lines, used for defect inspection of SiC substrates, epitaxial wafers, and etched wafers. After two years of unremitting efforts, the design team has overcome core key technologies in optical inspection such as laser scattering and microscopic imaging. The equipment adopts multiple inspection methods including differential interference contrast, photoluminescence, and dark field. Wafer inspection can be processed in parallel with data analysis, and wafer defects can be correlated with device failures. It features low-noise and high-resolution imaging, high inspection throughput, high detection rate, and accuracy, meeting the demand for improving SiC device yield. With the support and guidance of national, provincial, and municipal industrial policies, CETC Fenghua has accelerated technological research, launched SiC defect inspection equipment, filled domestic gaps, broken international monopoly, realized import substitution, actively responded to the urgent needs of China’s third-generation semiconductor industry development, and solved the “bottleneck” technical problems. Domestic Equipment Enables Optical Detection of Dislocations and Micropipes On June 21, YouRuipu, a domestic semiconductor front-end process metrology equipment company, announced the delivery of its SiC automatic optical dislocation and micropipe inspection equipment, the SICD series, to customers. As an important wide-bandgap semiconductor material, silicon carbide has advantages such as high critical breakdown field strength, high thermal conductivity, and high electron saturation drift velocity. High-temperature and high-power devices manufactured using it exhibit superior mechanical properties, physical and chemical stability, and other characteristics. During homoepitaxial growth on SiC substrates, dislocation defects in the substrate can extend and transform into the epitaxial layer, leading to a large number of extended defects in the epitaxial layer. Detecting the density and distribution of different types of dislocations and micropipe defects is a crucial step in SiC substrate manufacturing. Currently, dislocation defect inspection of SiC substrates is usually performed after etching. Existing dislocation and micropipe inspection equipment on the market has extremely slow detection speeds, often taking several hours to inspect an entire wafer. In actual production, the dislocation defect density is often measured selectively in partial areas of the wafer rather than across the entire wafer, making it impossible to detect the overall dislocation distribution of the wafer or match the automated production system of SiC substrates. YouRuipu’s SICD series equipment has four significant advantages: first, it realizes full-area scanning and detection of the entire substrate. Second, the detection imaging has high resolution, greatly improving detection accuracy. Third, while achieving full-wafer detection and high resolution, the detection efficiency has been increased by dozens of times—an entire wafer can be inspected in 10 minutes, with automatic output of inspection reports. Fourth, the SICD series integrates etched wafer dislocation defect detection and substrate high-resolution micropipe defect detection into a single device, allowing customers to use the equipment more effectively in production lines. “The SICD series equipment uses high-resolution real-time focusing high-speed scanning imaging technology and adopts deep learning algorithms (AI) to effectively improve the accuracy and speed of defect detection, helping to improve SiC manufacturing processes and production quality control,” said Dr. Tang Deming, General Manager of YouRuipu. The SICD series includes the semi-automatic inspection equipment SICD200s with manual loading/unloading and the fully automatic inspection equipment SICD200 with automatic loading/unloading. The latter can interface with the MES system of SiC substrate factories to realize factory automated production. Domestic 12-inch Online Epitaxial Film Thickness Metrology Equipment to Be Delivered Soon Recently, Gaize Semiconductor announced that its independently developed 12-inch metrology equipment, GS-A12X, is即将交付. This equipment is China’s first 12-inch online epitaxial film thickness metrology device, capable of accurately measuring epitaxial film thickness of various wafer materials while ensuring measurement precision and safety. Wafer preparation includes two major processes: substrate preparation and epitaxy. Epitaxy refers to the growth of a new single crystal layer on a single crystal substrate. The epitaxial process may be affected by various conditions, leading to uneven thickness, such as substrate temperature, reaction chamber pressure, reactants, and wafer surface cleaning. If uneven epitaxial thickness is located in the active area of transistor devices fabricated on the wafer surface, it will cause device failure. Therefore, it is particularly important to use film thickness measurement equipment to measure the thickness uniformity of the epitaxy after wafer preparation via the epitaxial process. GS-A12X uses a walking-axis dual-arm clean robot, and the measurement unit uses a newly designed Stage platform, which can choose between adsorption or clamping methods to maximize compatibility with customer application scenarios. The cooperation between the dual-arm robot and the Stage increases the measurement efficiency of GS-A12X by at least 30%; the application of an air-floating platform reduces the impact of vibration on measurement, making measurement data more stable; the overall modular design of GS-A12X reduces development cycles, improves assembly efficiency, shortens equipment maintenance time, and customized design makes GS-A12X better understand customer needs. Based on FTIR infrared spectroscopy technology, the equipment can monitor real-time data during wafer epitaxial manufacturing and provide high-precision test results. Its main features include the following: - Efficient and fast: Adopts rapid scanning technology, enabling high-precision test data to be obtained in a short time, improving production efficiency; - Non-intrusive detection: Uses infrared spectroscopy technology, which does not cause any damage or impact to the wafer, ensuring real and reliable test data; - High reliability: Uses high-quality materials and advanced technology to ensure equipment stability and reliability; - Data analysis: The equipment comes with data analysis software, enabling data visualization to help users better understand wafer performance and characteristics; - Customized function development: Developed for customer application pain points, making the system better understand customers. The equipment to be delivered this time adds Online technology. It complies with SEMI standard protocols and can seamlessly connect to customer OHT/MES and other systems. At the same time, the equipment realizes automated detection control, with intelligent control and automated operation functions, reducing labor costs and improving production efficiency. Sources: Wang Shuyi, Semiconductor Industry Observer, Wide Bandgap Alliance, Xinzhixun